1. Field of the Invention
This present invention relates to data communication systems and, more specifically, to the compensation of baseline wander phenomenon in baseband transceiver systems.
2. Description of the Prior Art
During the last two decades, the dramatically increasing computing power in PCs and the widespread popularity of Internet applications result in a continuously rising demand for vast and rapid data processing, storage and communication. To serve the demand on raising transmission data rate between users, Ethernet technology evolves, since the 1990s, from 10 Mbps Ethernet to the emerging 10 Gigabit (10G) Ethernet. Based on different application environments and commercial targets, the IEEE 802.3 task force has established a variety of standards to expedite the Ethernet development in many areas. Now the application of 100Base-TX Fast Ethernet in local area networks (LANs) has become one of the most prevalent approaches to achieve high-speed data exchange between neighbor computers and electronic appliances. As 1000Base-T Ethernet will be substituted for 100Base-TX Ethernet as the standard equipment in next-generation computer systems, the aggregate bandwidth of current backbone networks could be the bottleneck in constructing the future information superhighway. Therefore, to meet the requirement of supporting more bandwidth in data transmission, the IEEE 802.3an working group set about defining a new 10 Gb/s transceiver that would support links of up to 100 meters on category 6 or 7 copper wires [see IEEE Draft P802.3an/D3.0]. The 10GBase-T Ethernet standard is going to be approved in the mid of 2006 and its application will be realized in data centers in its initial phase to provide sufficient bandwidth in backbone networks for the coming 1000Base-T Ethernet era.
A brief block diagram of 10 GBase-T Ethernet transceivers is shown in FIG. 1. The 10G system supports operation over 4-connector structured 4-pair, twisted copper cabling at the transmission rate of 800 megasymbol/s on each pair where each symbol represents 3.125 bits. It only supports full duplex operation on each pair. Accordingly, a hybrid 10 is used to couple the transceiver to and from the copper wire 11 for each pair. The 10G transceiver comprises two parts: one is the transmitter that encodes and modulates the data from a host and then sends the modulated signals to a remote end; the other is the receiver that demodulates and decodes received signals and passes these restored data to the host. In the transmit path, Media Access Control (MAC) unit 12, in charge of processing requests from the host and managing the link, delivers data blocks to the physical layer of the transceiver through the XGMII interface 13. Then the physical coding sublayer (PCS) 14 of the physical layer scrambles the data bits from the MAC unit 12, encodes the scrambled bits by a low-density parity-check (LDPC) encoder and finally maps every 7 bits of the encoded output bit stream into 2 16-level pulse amplitude modulation (16-PAM) symbols. The 16-PAM technique is used to transform data bits into a set of predefined amplitudes to increase transmission efficiency in a bandlimited channel. The 16-PAM symbols are further processed by a Tomlinson-Harashima Precoder (THP) 16, which pre-equalizes signals prior to transmission to compensate the signal loss and distortion in a frequency-selective channel. Furthermore, the digitized symbols after pre-equalization are converted into continuous-time analog waveform by a digital-to-analog converter (DAC) 18 and then filtered by an analog filter 20 to roll off the high frequency spectral response to limit high frequency emissions. Eventually, the line driver 22 pushes analog waveform across the hybrid 10 and copper wire 11 to its opposite receiver.
In the receive path, the hybrid 10 couples signals on the copper wire 11 to the 10G receiver, and then the front-end analog filter 24 removes the high-frequency signal components lying out of the interest band to prevent the sampled data at the posterior analog-to-digital converter (ADC) 28 from aliasing. Before the ADC samples signals, a programmable gain amplifier (PGA) 26 is employed to adjust the range of input amplitude not beyond the acceptable maximum input amplitude of the ADC 28. Therefore, the following ADC 28 can sample and quantize incoming analog waveform and output digitized samples to the feedforward equalizer 29 without unwanted clipping noise. Subsequently, the feedforward equalizer 29 processes the digitized output samples by whitening the noise that added in the received signals during transmission and canceling residue intersymbol interference (ISI) to enhance the signal-to-noise ratio (SNR) at the equalizer output. After equalization, the equalized symbols are further passed to the receive unit in PCS (not clearly shown in FIG. 1) in which these symbols are transformed into a sequence of data bits, decoded by a LDPC decoder and de-scrambled to recover its original data blocks. Finally the information bits are sent to the host if the MAC layer validates these data blocks from the PCS.
As shown in FIG. 1, the copper wire 11 and the Ethernet transceiver are joined together by the hybrid 10 to support full duplex operation. Therefore, when signals are sent from the transmitter to an opposite receiver, they will pass through a cable and two hybrids 10 at least before detected by the receiver. These hybrids 10 used in the 10G Ethernet application are usually transformers whose frequency response is high pass in nature; thus transmit energy below the cutoff frequency of transformers will be lost. As the result of the indigenous high-pass characteristic, an undesired effect of channel on the transmitted waveform that is commonly termed “baseline wander” (BLW) comes about as the line code used in the baseband transmission systems is DC unbalanced. Once the BLW phenomenon occurs, the baseline of transmitted signals will be shifted up or down based on the polarity of the previous and present transmitted symbols. If symbols with consecutive positive or negative polarity are transmitted over a short time interval, the transformer will block such significant low-frequency energy borne in the transmitted signals that the resultant signal waveform may suffer clipping at the receiver and induce bit errors, even for short line lengths. For the reason, the receiver must compensate for the BLW phenomenon.
The previous techniques for canceling BLW phenomenon in baseband communication systems are listed below:    [1] Mel Buzes, “Method an apparatus for reducing baseline wander”, U.S. Pat. No. 6,140,857, Mar. 29, 1999.    [2] Leon Chia-Liang Lin and Gerchih Chou, “Automatic gain control for communication receivers,” United States, Patent US 2003/0142659 A1, Jan. 25, 2002.    [3] I. Greiss and E. Lida, “Digital base-band Receiver,” United States, U.S. Pat. No. 6,618,436 B2, Sep. 9, 2003.    [4] Sren A. Raghavan, “Digital baseline wander correction circuit,” U.S. Pat. No. 6,415,003 B1, Sep. 11, 1998.    [5] Jyh-Ting Lai, “Receiver for baseline wandering compensation,” United States, Patent US 2003/0206604 A1. Jul. 12, 2002.    [6] J. H. Baek, J. H. Hong, M. H. Sunwoo and K. Y. Kim, “EFFICIENT DIGITAL BASELINE WANDER ALGORITHM AND ITS ARCHITECTURE FOR FAST ETHERNET,” in Proc. IIEEE Signal Processing Systems, 2004    [7] US Patent/Publication No. 6433608; 6140857; 6415003; 6618436; 20030142659; 20030206604.
These techniques can be classified into three groups. The first one [1] is that the BLW is estimated and compensated in an analog domain as shown in FIG. 2. It comprises a BLW compensator 30, an ADC 32, a feedforward filter (FFF) 34, an adder 35, a slicer 36 and a feedback filter (FBF) 38. Although canceling the BLW in the analog domain looses the design requirement for ADC 32, the power consumption and the required area in chips are relatively large when compared to those in the digital compensation methods [3]-[6]. To improve the first method, C. L. Ling and G. C. Chou in [2] proposed another method that estimates the BLW in the digital domain and cancels it in the analog domain. It comprises a BLW compensator 30, an ADC 32, a FFF 34, adders 35, 37, a slicer 36 and a FBF 38. While this method may offer a good scheme to reduce the BLW, the closed-loop latency between the estimation and the removal of BLW, which is shown is FIG. 3, is too long to easily maintain the stability of the loop. In addition, additional hardware, such as a digital-to-analog converter and a low-pass filter are required for removing the BLW in the analog domain.
The third group implements the BLW estimation and cancellation functions only in the digital domain. The BLW compensator [3] shown in FIG. 4 includes a BLW compensator 30, an ADC 32, a FFF 34, an adder 35, a slicer 36 and a FBF 38. The BLW compensator 30 includes a delay unit 301 and an adder 303. As shown in FIG. 4, the BLW compensator [3] includes a simple pre-coding section that subtracts each received sample from a preceding sample to generate corrected data. This pre-coder compensates the BLW with relatively simple hardware and minimizes the interaction between the FFF 34 and the BLW compensator 30. However, because only two symbols, the present and the previous symbol, are utilized to estimate the BLW, errors may happen in removing the DC offset when the incoming symbols have insignificant DC components. This may lead to a catastrophic effect that removing the normal signals by using incorrect estimation. The other digital approaches are presented in [4]-[6], whose architectures are briefly illustrated in FIG. 5. It includes a BLW compensator 30, an ADC 32, a FFF 34, adders 35, 37, a slicer 36, a FBF 38 and a BLW estimator 39. These digital compensators all estimate the DC offset by using error signals generated from the difference between the output of the decision device (slicer 36) and either the input (the dotted line) or output (the solid line) of the FFF 34, and then compensate the BLW before (the dotted block) or after (the solid block) the FFF 34. These existing digital compensators are efficiently implemented in current digital circuit techniques.